Reference Number: ARL-SRP-00070

Project Description

In this project, students will be helping design Verilog logic for different Army chip design efforts, including AI hardware and digital signal processing. Students will design digital circuits in Verilog, write testbenches for those designs, and simulate those testbenches using Verilator and Cadence Xcelium. The updates and designs students work on will be used in future ARL chip designs.

Technical Skills

• Artificial Intelligence/Machine Learning
• Electrical Engineering Electronics
• Python, Verilog simulation (Cadence Xcelium, Verilator, ModelSim, iverilog, etc.), Git, Linux